In order to realize the downsizing and higher-density assembly of a semiconductor device, a semiconductor package having a plurality of semiconductor chips sealed in one package has been in practical use. When a cost reduction or the like of a semiconductor package is given higher priority, a lead frame is used as a circuit base on which semiconductor chips are mounted. In a semiconductor package using a lead frame (TSOP or the like), a plurality of semiconductor chips are stacked in order on the lead frame. Electrode pads of the semiconductor chips are electrically connected to inner leads of the lead frame via metal wires.
When a plurality of semiconductor chips different in size are mounted in a stacked manner on one surface (for example, a rear surface) of a lead frame, inner leads cannot be led to the vicinity of electrode pads of the upper small chip due to the shape of the lower large chip. This makes it difficult to connect the electrode pads of the upper small chip and the inner leads by metal wires. In particular, when chips are greatly different in shape like a memory chip and a controller chip forming a semiconductor memory device, it is difficult to connect the small chip (controller chip) and inner leads. Nor is it possible to directly connect the semiconductor chips to each other by metal wires in an electric circuit manner.
To solve these problems, it has been considered to stack a relay substrate and a small chip in order on a large chip or to dispose a relay substrate and a small chip on a large chip. The upper small chip is connected to the relay substrate via metal wires, and the relay substrate is connected to the lower large chip and inner leads via metal wires. The connection structure using the relay substrate becomes a factor of increasing manufacturing cost and manufacturing man-hours of a semiconductor device. Moreover, since the relay substrate is thicker than the semiconductor chips, the number of mountable semiconductor chips (the number of stacked layers) is reduced by the thickness of the relay substrate.
In order to increase the number of mountable semiconductor chips, it has been considered to mount semiconductor chips on both upper and lower surfaces of a lead frame. JP-A 11-040738 (KOKAI) describes a semiconductor device in which semiconductor chips different in size are mounted on both upper and lower surfaces of a chip mounting portion (die pad) of a lead frame. JP-A 2001-144247 (KOKAI) describes a semiconductor device in which semiconductor chips having the same shape are mounted on both upper and lower surfaces of a lead frame. In the above patent documents, an ordinary bonding structure is employed and no consideration is given to the connection of a small semiconductor chip and inner leads.